1. Technical Field
The present invention relates to a system-in-package (SIP) and a fabrication method thereof, and more particularly, to a stack-type package wherein a plurality of electronic devices are buried or stacked on a substrate such as a wafer.
2. Discussion of Related Art
Integration technology for semiconductor devices on a substrate has been continuously developed in order to reduce the size of a system and increase the integration density of semiconductor devices. A system-on-chip (SoC) has been introduced, in which a large number of circuit components are integrated on one chip. However, the SoC, which is configured by stacking various circuits on one single chip, has a technical limit in enhancing circuit integration. Recently, various stack-type structures, such as system-in-package (SiP), system-on-package (SoP), package-on-package (PoP), multi chip package (MCP) and the like, have been suggested as alternatives to overcome the technical limitation of system integration.
Recently, MCP technology of stacking a plurality of memory chips into one package realized a high-capacity package by fabricating even 16-stack memories. While the MCP technology is about stacking only memories, the SiP, SoP, PoP and the like are fabricated by Integrating memories and non-memories such as system LSI, ASIC, passive device and so on. In the SiP, SoP, PoP and the like, respective layers having various functions are stacked together or are connected to one another from side to side. In the SiP, a plurality of circuits configured as individual chips are connected to one another from side to side such that they are mounted as one package.
Studies on integrated packages such as the MCP, SiP and the like have been rapidly conducted at home and abroad. As requirements of high-performance and thin portable communication devices are increased, demands on the market for state-of-the-art integrated packages are increased. Particularly, as requirements of small, multi-functional and slim application products, such as mobile phones, PDAs, DSCs and the like, are increased, attempts have been actively made to bury passive and active devices in a package substrate or main board.
In a conventional integrated package, a buried stack structure is fabricated through a sequential build-up method of laminating an insulating material such as resin on a package substrate or main board, forming a hole in the package substrate or main board such that a device can be buried in the hole, burying an active or passive device in the formed hole, and then forming an interlayer dielectric on the insulating material.
However, since burying and stacking processes are performed on a package substrate or main board in the package by the burying and build-up method, there is a limit in reducing the size of a device corresponding to a fine pitch. Further, since a redistribution process for electrical connection between embedded chips should be essentially added due to the limit of a fine pitch to be applied, time for processing and fabrication cost are increased.
Furthermore, when a semiconductor device for high-speed operation, and the like are embedded in a package, a problem of heat radiation, etc. are inevitably raised. However, since there is a limit in solving the problems due to its structural feature, it is difficult to stably operate the device.